Boutekkouk, Fateh2022-04-282022-04-282013http://hdl.handle.net/123456789/13051In this paper, we present our flow that permits Maude specification generation from VHDL code. Firstly, a XML like Intermediate Format (IF) is created showing VHDL structures and statements in a hierarchical form. This format is an abstraction of the original VHDL code. Secondly, a Maude code is generated from this IF. Both Hardware system Maude specification and properties are then passed to the Maude model checker for verification purpose. Our idea is thus to combine between VHDL simulation and Maude based formal verification capabilities for hardware systems validation. The impetus behind this cooperation between simulation and formal verification is to enable hardware designers to discover errors that could not be detected by VHDL discrete event simulator.enVHDLMaudeSimulationFormal specificationFormalArticle