A Comparative study on scaling sapabilities of Si and SiGe Nanoscale double date dunneling FETs
| dc.contributor.author | Dibi, Zohir | |
| dc.contributor.author | Bentrcia, Toufik | |
| dc.contributor.author | Djeffa, Fayçal | |
| dc.contributor.author | Ferhati, Hichem | |
| dc.date.accessioned | 2022-05-05T01:55:08Z | |
| dc.date.available | 2022-05-05T01:55:08Z | |
| dc.date.issued | 2019 | |
| dc.description.abstract | In the last few years, an accelerated trend towards the miniaturization of nanoscale circuits has been recorded. In this context, the Tunneling Field-Effect Transistors (TFETs) are gaining attention because of their good subthreshold characteristics, high scalability and low leakage current. However, they suffer from low values of the ON-state current and severe ambipolar transport mechanism. The aim of this work is to investigate the performance of SiGe nanoscale Double Gate TFET device including low doped drain region. The electrical performance of the considered device is investigated numerically using ATLAS 2D simulator, where both scaling and reliability aspects of the proposed design are reported. In this context, we address the impact of the channel length, traps density and drain doping parameters on the variation of some figures of merit of the device namely the swing factor and the ION/IOFF ratio. The obtained results indicate the superior immunity of the proposed design against traps induced degradation in comparison to the conventional TFET structure. Therefore, this work can offer more insights regarding the benefit of adopting channel materials and drain doping engineering techniques for future reliable low-power nanoscale electronic applications. | ar |
| dc.identifier.uri | http://hdl.handle.net/123456789/13076 | |
| dc.language.iso | en | ar |
| dc.publisher | Springer | ar |
| dc.subject | TFET design | ar |
| dc.subject | SiGe alloy | ar |
| dc.subject | Scaling | ar |
| dc.subject | Interface traps | ar |
| dc.title | A Comparative study on scaling sapabilities of Si and SiGe Nanoscale double date dunneling FETs | ar |
| dc.type | Article | ar |